The semiconductor industry is full of innovations which are well documented in patents. A patent is not only a legal document that gives the inventor the right to stop others from using the invention without prior agreement, but it is also a huge resource for technical know-how. The process of obtaining a patent requires time, energy, technical expertise, and plenty of financial resources. Unfortunately, not all patents make it to production nor see their concepts materialized into a commercial product. The discussion here is not about patents that are written to increase the volume in a portfolio, but rather about the “quality patents” that are targeted to solve a problem with the idea of having a direct business justification. Most patents do not see the light of day not because they are not technically sound, but rather because they are not economically feasible.
IP analysts often encounter forward looking patent portfolios which are ahead of the industry and are often asked to provide an opinion on whether these patents will have a value in the coming future or not. To provide such feedback, the technology trends and market news need to be investigated. For semiconductor manufacturing related patents, the situation is complex because the technology changes rapidly and the industry tends to accept only incremental changes, as a totally new concept would require additional tools or new processes, which could turn out to be cost prohibitive. Therefore, patents which are radically different from the mainstream process are often categorized as being low value patents. Thus, it's extremely critical to do a thorough analysis of disruptive patents before labelling their value. It happens that sometimes patents that are deemed too far-fetched at a certain stage become economically feasible in a later period because either the dynamics have changed, or some additional constraints have propped up, or even a novel technology may have completely changed the scenario!
The semiconductor industry has seen many disruptive technologies in the past years which have initiated other changes, sometimes even among adjacent technologies. One such example is the finFET transistor introduced by Intel in 2011-2012. In a finFET process all the fins are aligned and all the gates are perpendicular to the fins. Due to design constraints, gates and fins must be cut. The general process is that first the fins are made and then a sacrificial poly-Si gate, or also known as a dummy gate, is formed. The gate-cuts are later performed according to the design requirements. After which, the sacrificial gate is removed, and the replacement gate is deposited exactly in the spot where the dummy gate previously existed. Ever since this gate-cut process in the sacrificial gate was established, patents started appearing suggesting that it would be more advantageous to do the gate-cut after the formation of the replacement gate. These patents never gained attention as most analysts or engineers believed that the metal patterning is more challenging. It is interesting to note that before the nineties, aluminum patterning was the only way to form interconnects until IBM introduced the Cu-Damascene process, where trenches are etched into a dielectric layer and then filled with copper. This new Damascene process enabled the formation of multi-layered dense interconnect structure, which is to this day critical to many semiconductor devices.
All the finFET manufacturers used the above-mentioned gate-cut process, as did TSMC for three generations (16 nm, 10 nm, & 7 nm), which is gate-cut before the replacement metal gate (GC-Before-RMG). But for the 5 nm node they decided to use the gate-cut after the replacement metal gate (GC-After-RMG) was completed. Figure 1 captures the GC-Before-RMG and GC-After-RMG processes for the 7 nm and the 5 nm finFET process respectively. In the GC-Before-RMG case, the high-K dielectric layer and the work function layers are present along the side walls of the cut, which is indicated by the dotted lines in the image on the left side. The dotted lines are used only as a guidance to give an approximate idea of where the work function layers are present.
Figure 1: TSMC’s gate-cut process in 7 nm & 5 nm nodes analyzed at UnitedLex
The image on the right in figure 1 shows the image of the GC-After-RMG process. According to TSMC’s patent, there is an insufficient process window in the GC-Before-RMG because after the poly-Si gate is cut, when the poly-gate is removed and the high-K dielectric material is deposited, the high-K layer is also present on the sidewalls of the cut, thus there is less of an opening available to fill the space for work function layers and the metal fill. Therefore, TSMC decided to opt for the GC-After-RMG process. Here, the presence of dielectric and work function layers are not seen along the sidewall of the gate-cut as is confirmed from the absence of the dotted zone along the cut interface.
This is an example, where a concept which looked impractical a few years back, became the only way forward for the current technologies. If metal patterning in small dimensions is back as a mainstream process, then what does it imply for interconnects where narrow and small dimensions of metal lines are constantly required for advanced technology nodes? Can a concept developed for the front-end of line be applied to the back-end-of-line? A look into the patents filed post 2020 related to metal interconnect formation suggests that most manufacturers are considering metal patterning as an option for future technology nodes.
Figure 2 elaborates the currently used Cu-Damascene process and the new subtractive metal patterning process. The two processes are distinctly different. In one case, dielectric material is etched and the gaps are filled with metal, while in the other case, metal is patterned, and the gaps are filled with dielectric material.
Figure 2: A simplified scheme of Cu-Damascene & subtractive metal patterning process
Both diagrams are overly simplified. In both cases, more than one patterning step is needed to arrive at the result.
One might ask how this is different from the old aluminum patterning and why should the industry accept subtractive patterning or rather why not simply stick with the Damascene process? The basic idea of subtractive patterning is like the old metal patterning, but the situation is very different. The line widths and spacing are very small. The dielectric surrounding the metal lines are low-k and or may even have air gaps, so it is extremely critical that the dielectric material is not damaged during the etching process, which occurs during the Damascene process. Also, patterning narrow interconnect structures requires complex hard mask stacks consisting of different materials, which require multiple etching chemistries, not to forget that hard mask stacks increase the cost and processing time. In subtractive patterning the metal lines could be copper with barriers or new materials that do not need barrier layers like ruthenium. Relative concepts are already being presented in technical forums. The successful implementation of metal gate-cut in large volume with optimized lithography and etching processes without any over-etching or misalignment issues, would give confidence to implement metal patterning for interconnects in the future technology nodes.
The method of transposing a novel concept designed for a specific application and applying it to another application is constantly seen in the semiconductor industry and in other industries. In the IP world it is termed as applicability to an adjacent technology. The word “adjacent” could imply an extension of the same product or it even a very distant application. The capability of correlating disparate applications with the same inventive concept requires ingenuity and improves applicability of the patent. Currently, there are several discussions surrounding the question: can artificial intelligence (AI) file patents or not? It would be interesting to see if AI could formulate patents that would be applicable to various adjacent technologies. One thing is certain, in the future, thinking out of the box will not be a rarity but the new norm.
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