Finding golden patents starts with sifting
Daily there are IP news stories about companies settling IP license agreements, filing PTAB petitions or appealing to federal circuits. These patents that are licensed or litigated are considered “golden patents”—usually from the plaintiff—because they clearly drive value worth protecting. However, they are usually one of many, buried in a portfolio amongst patents that are never discussed nor implemented in commercial products.
This leads to the key questions:
- What is a golden patent?
- How can you detect and evaluate golden patents in a portfolio?
Many sophisticated algorithms have been written to find golden patents and estimate their value. Most of the algorithms are based on multiple parameters like forward citations, backward citations, prosecution length, filing date, inventor profile, technology relevance and market coverage. However, the true test to verify a golden patent comes when it is licensed or litigated because these cases solidify their “Evidence of Use” (EoU) and market value.
EoU can be obtained through reverse engineering, publicly available documentation, functional testing or through a discovery process. A crucial element to the process is that it must always be coupled with an analysis of the technology’s relevance in the market because the saturation of competitors has a direct correlation with the claim scopes. A patent cannot be considered “golden” if it is one of thousands within the field unless it has a very early priority date. A golden patent must have well-defined claims in relation to a high-volume product that drives considerable revenue.
Crossover of the patent’s utility between technologies adds an additional layer of complexity in defining, or finding, golden patents. “Market Relevance & Industry Use” along with “Infringement & Detectability” are important parameters to evaluating a patent. However, some experts argue that a patent could be golden for a specific technology but not golden in an adjacent technology. Is this true?
Let’s look at 3D NAND devices to answer the question.
Understanding adjacent technology and markets with 3D NAND devices
Looking at patents related to stacked monolithic devices in the semiconductor industry clarifies the concept of adjacent technologies. In monolithic devices, there are different layers stacked on top of each other and each layer has a functional device. Originally, monolithic devices meant that these stacked layers containing functional devices were grown on top of each other. Today the definitions are blurred and often 3DIC devices with bonded substrates are also considered as monolithic devices, like seen in some image sensors. This monolithic concept was suggested as an alternative to scaling in advanced logic by several IDM players. If monolithic patents were to be evaluated with the two parameters discussed earlier, on logic devices, then they would be rated as potential patents but not yet golden.
However, similar concepts were introduced in the memory industry. Back in 2017, Intel introduced XPoint memory, which had a top cell stacked over a bottom cell. The monolithic concept got its reinforcement when Intel/Micron introduced their 3D NAND with 96 layers having their CMOS circuitry under the memory array (CuA). On Intel’s heels, SK-Hynix introduced their 3D NAND devices with 96 layers having their periphery under CMOS (PUC). The figure 1 shows the cross-section of SK-Hynix 3D NAND with 128 layers. The periphery under the memory cell has its own transistors and metal interconnects, so does the memory cell which is on top of the periphery structure.
Figure 1: SEM cross-section of 128-Layer 3D NAND of SK-Hynix, showing the periphery under the memory cell
Thus, a 3D NAND structure with a periphery under the memory cell seems to satisfy the condition of stacked monolithic devices, but can FLASH memory be called an adjacent technology? Not really, because both memory and logic devices are based on transistors having gates, source and drain structures. Also, they are both made of Si and work on CMOS principles, meaning they are not different technologies but at most different applications, or adjacent markets, working on the same technological principles.
One example of adjacent technology would be induction heating and resistive heating. Both require a current to heat up a resistive element, however the current generation mechanism can be completely different for each of them. In one case, the current may come from a power source such as a wall outlet or battery, while in the other case, the eddy currents are generated by magnetic induction. Adjacent technologies should be strictly thought of as two different technologies that are used for similar applications.
The concept of adjacent technology is often not well defined and often incorrectly used synonymously with “adjacent markets.” Generally, a patent considered golden for a specific technology would still be considered golden in another application that uses the same underlying technology. That is why when looking for EoU instead of focusing on a narrow domain, it is important to also investigate other applications in the same industry where similar principles are used.
Challenges of 3D NAND devices and future patents
The most challenging task of evaluating a portfolio comes with discussing future patents. One way of evaluating these patents is to follow the technology trends in a specific field, staying current with every modification in every generation, and speculating what new changes may be introduced. However, there will always be patents that disrupt the game with novel solutions. Therefore, it is always safer to bet on patents that explore new problems within existing configurations used for upcoming generations.
Once again looking at 3D NAND, most manufacturers believe the devices can be made with greater memory density by simply increasing the layers. By keeping their existing configuration and process flow they can minimize R&D costs. Nevertheless, 3D NAND will still encounter unexpected problems in future generations.
Dive deeper with wordline structures
One obvious problem is the wordline contact structures. Each memory cell shown in figure 1, extends horizontally into the page and each of these cells needs to be contacted by conductive contact structures to supply voltage to each cell. These contacts to the cells are known as wordline contacts. As the cells or layers increase, the implementation of wordline contacts becomes more challenging. To facilitate contact to cells, most manufacturers have adopted some variant of two directional staircases. The formation of the staircase at its base is already extremely demanding. First a stack of bilayer dielectrics is deposited, then the staircase is patterned, next one dielectric layer is removed and finally replaced with a conductive layer. With this clever technique, patterning of conductive layers is avoided.
Figure 2 shows the wordline contacts for the 128-layer SK-Hynix 3D NAND and a diagram of the bi-directional staircase. The yellow pads are conductive materials, and the blue lines are dielectric materials.
Figure 2: SEM cross-section of wordline contacts along with a diagram of a bi-directional staircase for wordline contacts
In the future, as the layers increase to a few hundred layers, the wordline contact formation could become a major ordeal. A looming problem is heat dissipation. As layers increase, the complexity of interconnect structure below and above the memory cells will also increase as well as the connections to global and local power lines. As these interconnect structures become dense and have more ramifications, they will require better heat dissipation.
There will also be challenges in the structural formations and operational changes. As the layers increase, the uniformity of read and write between top cells and bottoms cells could be different, thus the structure necessitates a more complex supporting circuitry.
These are only a few of the issues that may arise for the future 3D NAND devices, added to the existing challenges like patterning and depositions of many layers. In the case of 3D NAND, patents that propose a solution to future problems, such as those discussed above, could be considered high-potential—or golden.
Extracting patent gold
Finding high-potential patents from within a portfolio depends on understanding the technology and experience of patent analysts. Identifying golden patents is time-consuming, like panning for gold, which requires multiple sieves, specialized gadgets and patience. As in gold panning, where particles of gold with higher specific gravity are separated from the soil, in a portfolio, patents with a strong EoU potential are the heavyweights worth extracting.
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